1. Field of the Invention
This invention relates to the formation of integrated circuits which include gate conductor and diffusion regions which have self-aligned silicide (salicide) conductive materials and contacts to diffusion regions which are self-aligned (borderless) to the gate conductor regions.
2. Description of the Related Art
As the size of integrated circuits devices (such as semiconductor devices) decreases below the one-half or one-quarter micron range, conventional photolithographic techniques may not meet required tolerances. In response to this problem, a number of self-aligned methods (which do not rely upon masks or similar photolithographic techniques) have been developed to increase the density of integrated circuit devices.
One such self-aligned technique involves the formation of self-aligned silicides known as salicides. Silicides are formed from the thermal combination of silicon and a metal such as titanium, cobalt or tungsten. Silicides are used to reduce contact resistance and to reduce the resistance of localized regions of silicon.
Conventional salicide forming techniques place an insulator (e.g., oxide or nitride) between the metal and the silicon in areas where the silicide is not to be formed. Therefore, only in areas where the silicon directly contacts the silicon. The silicide will be formed. In this way, the silicide is self-aligned (e.g. is a salicide) and does not require conventional photolithographic techniques.
Another example of a self-aligned device which is used with field effect transistors in, for example, dynamic random access memory (DRAM) devices and which helps increase circuit density is a borderless (e.g., self-aligned) contact (SAC). Conventional field effect transistors (FETs) include a central gate stack over an underlying channel region, and peripheral source and drain regions adjacent the channel. Such self-aligned contacts make electrical connections between the FET and devices such as capacitors or bitlines and are self-aligned by the central gate stack structure.
Conventional salicide formation techniques form salicide over the top of the central gate stack structure and over the top of the source and drain regions. Such structures cannot be used with conventional borderless SACs because the salicide over the gate does not permit sufficient dielectric separation of the SAC and the gate. Thus, conventional structures which utilize both self-aligned contacts and salicide have a high defect rate because the salicide over the gate often forms a short circuit with the self-aligned contact. This short circuit problem essentially prohibits the use of self-aligned contacts over conventional gate structures which include salicide. Therefore, the miniaturization of such salicide devices is limited because the bitline contacts must be formed with conventional lithographic techniques and cannot be self-aligned.
It is, therefore, an object of the present invention to provide a structure and method for a field effect transistor for dynamic random access memory integrated circuit devices having a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor; and at least one self-aligned contact adjacent the gate conductor.
The invention also includes insulating spacers along a lower portion of the gate conductor, wherein the salicide regions are positioned between the insulating spacers and the gate cap along the sides of the gate conductor. Additionally, the invention has a source region and a drain region adjacent a base of the gate conductor, wherein the self-aligned contact forms an electrical connection with the source region or the drain region and there are second salicide regions above the source region and the drain region.
In one embodiment, a method of the invention includes forming an insulator over a gate conductor and a gate cap, etching the insulator to form spacers along a lower portion of sides of the gate conductor, forming a metal over the gate conductor, the gate cap and the spacers and heating the metal to form salicide regions along upper portions of the sides of the gate conductor in direct contact with the metal, removing the metal and leaving the salicide regions, and forming at least one self-aligned contact adjacent the gate conductor.
The etching includes over-etching the insulator sidewall spaces such that the upper portions of the sides of the gate conductor are exposed and come into direct contact with the metal. In addition, salicide regions are formed above the source region and the drain region of the field effect transistor. The self-aligned contact makes an electrical connection to the source region or the drain region of the field effect transistor.
The invention allows salicide devices to be used with self-aligned contacts. By permitting the salicide to be utilized with self-aligned contacts devices, the resistance of such self-aligned contact devices is substantially reduced when compared to conventional structures which either do not include the salicide devices or which do not include the self-aligned contracts.